| ISBN: ISBN: 0-8 186-8277-9
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| ISBN: ISSN: 1081-7735
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| ISBN: DOI: 10.1109/ATS.1998.741662
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| |
| description |
In mixed-mode BIST, deterministic test patterns are generated with
on-chip hardware to detect the random-pattern-resistant (r.p.r.)
faults that are missed by the pseudo-random patterns. While previous
work in mixed-mode BIST has focussed on developing hardware schemes
for more efficiently encoding a given set of deterministic patterns
(generated by a conventional ATPG procedure), the approach taken in
this paper is to improve the encoding efficiency (and hence reduce
hardware overhead) by specially selecting a set of deterministic
patterns for the r.p.r. faults that can be efficiently encoded. A
special ATPG procedure is described for finding test patterns for
the r.p.r. faults that are correlated (have the same logic value) in
many bit positions. Such test patterns can be efficiently encoded
with one of the many "bit-fixing" schemes that have been
described in the literature. Results are shown for different
bit-fixing schemes which indicate dramatic reductions in BIST
overhead can be achieved by using the proposed ATPG procedure to
select which test patterns to encode.
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| publisher |
Institute of Electrical and Electronics Engineers
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| type |
Text
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| Article in Proceedings
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| source |
In: Proceedings of the 7th Asian Test Symposium (ATS), Singapore,
December 2-4, 1998, pp. 492-499
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| contributor |
Rechnerarchitektur (IFI)
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| subject |
Reliability, Testing, and Fault-Tolerance (CR B.8.1)
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